Branch instructions

B.N (Branch) instruction modifies the PC register so that it skips to a different instruction
BLT.N conditional branching
- only modifies PC if the N bit in the APSR is set.
- the instruction to jump to is encoded within the instruction itself: 0xFC = -4, so jump back 4 instructions, from 0x8e to 0x8a
Branching results in pipeline delays –> solution e.g. loop unrolling

BL (branch and link)

BL saves the address of the next instruction into the LR link register .
- The previous value of LR (i.e. previous function return address) must also be saved somehow.
- The previous return address is saved to the stack .

Example of a main function executing (branching off into) the delay subfunction:

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int main(){
    GPIO_PORTF_DATA_BITS_R[LED_RED] = LED_RED;
    delay();	
    GPIO_PORTF_DATA_BITS_R[LED_RED] = 0;
}

	Disassembly	Register
Before `BL`
After `BL`

Notes:

After branching off into the subfunction delay, the stack is expanded by 4 memory units, as can be seen in the SUB SP, SP, #0X4 instruction.
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0xF0 - 0x4 = 0xEC
At the end of delay(), the reverse occurs. The stack is shrunk by 4 memory units: ADD SP, SP, #0X4 and points to 0xF0 again, just like before delay() was executed.
The return of the delay() function is given by the BX branch instruction .
It would be expected that, right after BL, LR stores the instruction address 0x94, but instead 0x95 is stored.
- This is also at odds with the fact that the ARM instructions must be aligned at even addresses.
- This is a legacy behaviour explained in the BX section .
- At the end of the subfunction (after executing BX), the PC register is indeed updated to the correct instruction 0x94.